TL;DR
An upstream PowerVR driver and new platform support were combined to enable hardware-accelerated 3D on the T-HEAD TH1520 (used in the Lichee Pi 4A), marking the first RISC‑V SoC with mainline GPU acceleration. The work required several new kernel drivers for mailbox, firmware protocol, power domains, clocks/resets and a pwrseq-based power sequencer, plus a Vulkan-native userspace stack using Zink.
What happened
Michał Wilczyński implemented and upstreamed missing platform pieces so the mainline drm/imagination PowerVR driver could run on the T-HEAD TH1520. The effort involved adding a mailbox driver (mailbox-th1520) to talk to the SoC’s E902 coprocessor, implementing the AON firmware protocol (thead-aon-protocol), exposing the GPU rail as a generic power domain (pmdomain-thead), and extending clock and reset support (clk-th1520-vo, reset-th1520). A time-sensitive GPU power-up sequence was handled by a new pwrseq-thead-gpu sequencer that dynamically acquires the GPU’s clocks and reset controls and enforces the required ordering. A small abstraction (pvr_power_sequence_ops) was added to the drm/imagination driver so the driver can select a pwrseq-based backend for the TH1520. Display scanout was handled by a separate Verisilicon DC8200 DRM effort led by Icenowy Zheng (patches in review), and userspace rendering was driven via a Vulkan-native Mesa path with Zink for OpenGL compatibility.
Why it matters
- Brings the first known RISC‑V SoC (TH1520) into the realm of mainline, hardware‑accelerated 3D graphics.
- Demonstrates how generic kernel subsystems (GenPD, pwrseq, clocks/resets) can be combined to support platform‑specific power sequencing without vendor-only blobs.
- Separating power sequencing into a dedicated pwrseq driver reduces platform logic in the GPU driver and enforces strict hardware ordering.
- Using a Vulkan-native driver plus Zink avoids implementing a legacy OpenGL backend, simplifying upstream graphics support for new GPUs.
Key facts
- Author: Michał Wilczyński; published metadata: 2025-12-30.
- Work enabled the PowerVR GPU on the T-HEAD TH1520 SoC, used in the Lichee Pi 4A.
- Mainline drm/imagination driver upstream merge culminated with Linux 6.18 (per the author).
- Platform drivers added or extended: mailbox-th1520, thead-aon-protocol, pmdomain-thead, clk-th1520-vo, reset-th1520, and pwrseq-thead-gpu.
- A pvr_power_sequence_ops abstraction (commit e38e8391f30b referenced) was added so the driver can use a pwrseq backend.
- Display output on the TH1520 uses a Verisilicon DC8200 display controller paired with a Synopsys DesignWare HDMI bridge.
- Display driver work for the DC8200 (led by Icenowy Zheng) is in review (v4) and was applied on top of mainline for the demo.
- Userspace rendering relies on a Vulkan-native Mesa PowerVR driver, with Zink providing OpenGL compatibility.
- The author used Linux 6.19 as the base for reproduction, with unmerged display controller patches applied on top.
What to watch next
- Merge status of the Verisilicon DC8200 display controller patches now in review (v4) — currently not in mainline per the source.
- Upstream acceptance and wider distribution of the pwrseq-thead-gpu sequencer into mainline kernel trees — not confirmed in the source.
- Progress enabling the same display IP on other RISC‑V SoCs (for example the StarFive JH7110) and how integration differences are addressed — not confirmed in the source.
Quick glossary
- DRM (Direct Rendering Manager): A Linux kernel subsystem that provides an API for graphics drivers, coordinating buffer management, modesetting and GPU access.
- Power Domain (GenPD): A kernel abstraction that represents independently controllable power rails or domains, allowing the system to turn hardware blocks on and off.
- pwrseq (Power Sequencing): A kernel framework to encode and run time-sensitive power-on/off sequences for hardware that requires strict ordering of clocks, resets and supplies.
- Vulkan: A modern, low-overhead graphics and compute API used for high-performance rendering workloads.
- Zink: A Mesa component that implements OpenGL on top of Vulkan, enabling OpenGL applications to run via a Vulkan driver.
Reader FAQ
Is this the first RISC‑V SoC with mainline hardware‑accelerated 3D?
According to the source, the TH1520 becomes the first RISC‑V SoC to feature fully mainline, hardware‑accelerated 3D graphics support.
Are the display controller patches merged into mainline?
No — the Verisilicon DC8200 display controller patches are in review (v4) and were applied on top of mainline for the demo.
Do I need vendor out‑of‑tree drivers to run graphics on the TH1520 now?
The work described enables mainline drm/imagination usage on TH1520; however, the display patches used for the demo were not in mainline per the source.
Is OpenGL supported natively on this stack?
The PowerVR userspace path is Vulkan‑native; OpenGL functionality is provided through Zink rather than a separate native OpenGL driver.
Igniting the GPU: From Kernel Plumbing to 3D Rendering on RISC-V How I enabled the PowerVR GPU on the TH1520 SoC by writing the missing kernel drivers. December 28, 2025…
Sources
- Igniting the GPU: From Kernel Plumbing to 3D Rendering on RISC-V
- Imagination PowerVR Driver With Linux 6.18 To Support …
- Michal Wilczynski: [PATCH v11 0/4] Add TH1520 GPU …
- Linux 6.17 Lands New Driver To Power On The T-HEAD …
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