TL;DR
V8's RISC-V port has been merged into the main repository and reached near feature parity with x86_64 and ARM64, with active testing and fast breakage fixes from the community. Recent engineering work simplified pool emission, eliminated a Wasm jump-patching race, added several performance optimizations using RISC-V extensions, expanded vector support, and deprecated the 32-bit RISC-V port pending use cases.
What happened
Over the past months the V8 team and RISC-V maintainers pushed multiple changes to the RISC-V backend now hosted in V8's primary repository. Pool handling was simplified by deferring emission of the constant pool to the end of code generation, reducing interplay between constant and trampoline pools and easing a future move of constants out of executable memory. A race in WebAssembly’s indirect-call jump-table patching was fixed by switching to a memory-backed target-load sequence that is atomically visible to other threads; the patcher chooses a shorter direct-jump sequence when targets are nearby. Performance work leveraged RISC-V Zba instructions: fused shift-add (shxadd) reduced address-calculation instruction counts in loads, and zext.w dramatically cut pointer-decompression cost. Vector (RVV) support was extended to larger vector lengths beyond 128 bits and validated on real hardware. Finally, the 32-bit RISC-V V8 port has been deprecated and will be maintained through May 2026 unless a strong use case appears.
Why it matters
- Simpler pool emission reduces compiler complexity and makes it easier to relocate constants into non-executable memory, improving safety practices.
- Fixing the Wasm jump-table race removes a subtle correctness bug where CPUs could execute inconsistent instruction fragments during patching.
- Use of RISC-V Zba instructions and zext.w yields measurable code-size and instruction-count reductions for common operations, improving performance.
- Broader RVV support enables SIMD-accelerated Wasm workloads on CPUs with larger vector lengths and helps run benchmark suites end-to-end.
- Deprecation of the 32-bit RISC-V port signals focus on 64-bit targets and may affect embedded projects that expected long-term V8 support.
Key facts
- The RISC-V port of V8 has been upstreamed to the main V8 repository and is largely at feature parity with x86_64 and ARM64.
- V8’s buildbots continuously test the RISC-V port; an independent Jenkins buildbot runs additional configurations.
- Trampoline pools handle long jumps; near-jumps use 13-bit offsets, so trampoline emission must be managed to keep targets reachable.
- Constant pools are now emitted at the end of code generation, removing cross-dependencies with trampoline pools.
- Wasm indirect-call jump table patching switched from a two-instruction constructed-target sequence to a memory-load-based sequence to avoid reader-side races.
- The patcher selects a direct 'jal' when the target is within range, otherwise it updates the memory target and then patches to an auipc-based sequence.
- Zba's shxadd is now used to collapse multiple address-calculation instructions into one, sometimes halving load instruction counts.
- Using zext.w reduced pointer-decompression from five instructions to two in a highlighted case.
- Vector (RVV) support was expanded beyond 128-bit lanes to 256 and 512 bits and tested on real hardware.
- RISC-V 32-bit support has been deprecated and will be kept until May 2026; removal is possible if no strong use case appears.
What to watch next
- Whether constants are actually relocated into a non-executable section (not confirmed in the source).
- Further micro-optimizations in the Wasm patcher and additional heuristics for choosing short vs. long patch sequences.
- Adoption and testing of RVV-enabled builds on more physical hardware and the impact on real-world Wasm workloads (not confirmed in the source).
Quick glossary
- V8: An open-source JavaScript and WebAssembly engine originally developed by Google, used in browsers and other runtimes.
- RISC-V: An open, extensible instruction set architecture (ISA) used in research, embedded, and general-purpose processors.
- Trampoline pool: A block of indirect jump or call stubs emitted near code to reach targets that are too far for short branch offsets.
- Constant pool: A sequence of literal values placed near code so instructions can load constants that cannot be encoded directly.
- RVV (RISC-V Vector Extension): An extension to RISC-V that provides vector (SIMD) instructions with flexible vector lengths for data-parallel computations.
Reader FAQ
Is the RISC-V port fully in the main V8 repository?
Yes; the RISC-V port has been upstreamed to V8’s main repository and is largely at feature parity with other supported architectures.
Was the Wasm jump-patching race fixed?
Yes; the patcher now uses a memory-backed load sequence or a direct 'jal' when suitable, preventing reader-side races.
Will constants be moved out of executable memory?
The change prepares for moving constants to a non-executable section, but an actual relocation is not confirmed in the source.
What is the status of 32-bit RISC-V support in V8?
The 32-bit RISC-V port is deprecated and will be maintained until May 2026; removal afterward depends on whether a strong use case appears.
Posted by: Florian Loitsch, Ji Qiu, Kasper Lund, Yahan Lu, Zhijin Zeng In 2020, Kim McMahon wrote a blog post where she announced the open-sourcing of V8 on RISC-V. At…
Sources
- A glimpse into V8 development for RISC-V
- The RISC-V World Sees Changes, Milestones, and …
- Progress Report on RISC-V Virtualization Technology
- Evaluating RISC-V's Path Across Data Centers, Automotive …
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